In custom ICs such as an ASIC (Application Specific Integrated Circuit) or the like, improvement in an operating speed is realized by transistor finer geometries. A gate delay time t is formulated as shown in the following expression (1), using a capacitance C, a voltage V, and a current I. That is, the gate delay time is proportional to a value obtained by dividing electric charge accumulated in the capacitance (=the capacitance C×the voltage V) by the current I.t∝C·V/I  (1)
When finer device geometries are achieved (e.g. when a channel length or a gate oxidization film thickness is reduced), each parameter of the capacitance, voltage, or current is reduced to 1/K according to a scaling rule (a proportional reduction rule). Thus, likewise, the gate delay time t can also be reduced to 1/K.
On the other hand, SRAMs (static random access memories) cannot reduce the delay time to 1/K just by achieving the finer device geometries. The following is a description about this.
A bit line delay time tb1, which constitutes a lot in the delay time of the SRAM can be formulated as in the following expression (2) using a bit line capacitance Cb1, a potential difference between a bit line pair ΔVb1, and a cell current Icell.tb1=Cb1·ΔVb1/Icell  (2)
With achievement of the finer geometries, the capacitance Cb1 and the cell current Icell can be reduced to 1/K according to the scaling rule (proportional reduction rule). On contrast therewith, the potential difference between a bit line pair ΔVb1 is a parameter determined by an offset voltage of a sense amplifier, and cannot be reduced with achievement of the finer geometries. Accordingly, the bit line delay time tb1 cannot be reduced to 1/K with achievement of the finer geometries.
As described above, a higher-speed operation of the SRAM cannot be performed just by achieving the transistor finer geometries. For this reason, in the conventional SRAM, by changing a memory configuration, the higher speed is achieved (refer to Non-patent Document 1, for example). When the number of cells per bit line is reduced to a half, the bit line capacitance Cb1 is also almost halved. As a result, according to the above expression (2), the bit line delay time tb1 is also likewise almost halved.
However, this design method increases the number of banks and the number of sensing circuits.
FIG. 8 is a diagram showing a typical configuration example of a conventional sensing circuit. Referring to FIG. 8, a memory cell array 801 includes memory cells arranged at intersections between a plurality of word lines not shown and a plurality of bit line pairs. A memory cell includes a flip-flop and two pass transistors (also referred to as “access transistors”). The flip-flop is constituted by cross-connecting inputs and outputs of two inverters. The two pass transistors are connected between a connecting node of the inputs and the outputs of the two inverters and respective bit lines of a bit line pair. Gates of the two pass transistors are connected in common to a word line.
Referring to FIG. 8, a bit line pair selection circuit 802 includes a pMOS transistor P101 with a source thereof connected to a power supply VDD and a drain thereof connected to a bit line BLT, a PMOS transistor P102 connected between a pair of the bit line BLT and a bit line BLN, and a PMOS transistor P103 with a source thereof connected to the power supply VDD and a drain thereof connected to the bit line BLN. Gates of the pMOS transistors P101, P102, and P103 are connected in common to a pre-charge control signal PC.
The bit line pair selection circuit 802 further includes an nMOS transistor N101, an nMOS transistor N102, an NOR circuit 811, a pMOS transistor P104, and a pMOS transistor P105. The nMOS transistor N101 is connected between the bit line BLT and a write data signal line WDT, which is one of a pair of the write data signal line WDT and a write data signal line WDN. The nMOS transistor N102 is connected between the other write data signal line WDN of the write data signal line pair and the bit line BLN. Two input terminals of the NOR circuit 811 are connected to a write control signal (write enable signal)/WE and a bit line pair selection signal /YS (also referred to as a “column selection signal”), and an output terminal of the NOR circuit 811 is connected in common to gates of the nMOS transistors N101 and N102. The pMOS transistor P104 is connected between a node SAT of a sense amplifier 803 and the bit line BLT. The pMOS transistor P105 is connected between a node SAN of the sense amplifier 803 and the bit line BLN. Gates of the pMOS transistors P104 and P105 are connected in common to the bit line pair selection signal /YS. The write control signal /WE and the bit line pair selection signal /YS become active at low levels thereof (of a ground potential GND). The bit line pair selection signal /YS is output from a column decoder not shown (for decoding a column address and selecting a bit line pair corresponding to the address).
Referring to FIG. 8, the sense amplifier 803 includes a pMOS transistor P204 with a source thereof connected to the power supply VDD and a drain thereof connected to the node SAT, a pMOS transistor P205 with a source thereof connected to the power supply VDD and a drain thereof connected to the node SAN, and a pMOS transistor P203 connected between the nodes SAT and SAN. Gates of the pMOS transistors P203, P204, and P205 are connected in common to a control signal RSE. Before or after read and write operations, the control signal RSE is driven low, and the nodes SAT and SAN are both set to the power supply voltage VDD. The sense amplifier 803 includes a pMOS transistor P201 with a source thereof connected to the power supply VDD and a drain thereof connected to the node SAT, a pMOS transistor P202 with a source thereof connected to the power supply VDD and a drain thereof connected to the node SAN, and nMOS transistors N201 and N202 with drains thereof connected to the node SAT and the node SAN, respectively, and sources thereof connected in common. Gates of the pMOS transistor P201 and the nMOS transistor N201 are connected in common to the node SAN. The gates of the pMOS transistor P201 and the nMOS transistor N201 are connected in common to the node SAN.
The sense amplifier 803 further includes an nMOS transistor N203 with a drain thereof connected to a common connecting node between the sources of the nMOS transistors N201 and N202 and an nMOS transistor N204 with a drain thereof connected to a source of the nMOS transistor N203, and a source thereof connected to the potential GND of a substrate. A gate of the nMOS transistor N203 is connected to a sense amplifier activation signal SAE (that is set to the power-supply potential of the power supply VDD when the sense amplifier 803 is activated). A gate of the nMOS transistor N204 is connected to the control signal RSE. The node SAT is connected to an input terminal of an inverter 812. An output terminal of the inverter 812 is connected to a gate of an nMOS transistor N205 with a drain thereof connected to a data output line DL and a source thereof grounded (or set to the substrate potential GND). The node SAN is connected to an input terminal of an inverter 813. When the sense amplifier activation signal SAE is set to the power supply voltage VDD and when the sense amplifier 803 is activated, the pMOS transistors P201 and P202, nMOS transistors N201 and N202 constitute a latch circuit. Then, an amplification operation as follows is performed: through an on-state transistor of the pMOS transistors P201 and 202 (the transistor with a gate thereof connected to one of the nodes SAT and SAN on a lower voltage side), the node on a higher voltage side is charged to the power supply voltage VDD. Through an on-state transistor of the nMOS transistors N201 and N202 (the transistor with a gate thereof connected to one of the nodes SAT and SAN on the higher voltage side), the node on the lower voltage side is discharged to the substrate potential GND.
When a read operation is performed, data stored in a selected memory cell (not shown) in the memory cell array 801 is output to a bit line pair BLT and BLN to which the selected memory cell is connected, and the potential difference ΔVb1 is generated between the bit line pair BLT and BLN after a certain time. In the bit line pair selection circuit 802, the bit line pair selection signal /YS is set to a low level (or the substrate potential GND), the pMOS transistors P104 and P105 are turned on, and the potential difference ΔVb1 between the selected the bit line pair BLT and BLN is transferred to the nodes SAT and SAN in the sense amplifier 803.
When the sense amplifier activation signal SAE is set to a high level (or the power supply voltage VDD), the sense amplifier 803 amplifies the potential difference ΔVb1 between the nodes SAT and SAN and outputs read data to the data output line DL. When the node SAT is at the substrate potential GND, an nMOS transistor N205 that receives an output of the inverter 812 (at the power supply voltage VDD) is turned on. Then, the data output line DL is set to the substrate potential from the power supply voltage VDD. On the other hand, when the node SAT is at the power supply voltage VDD, the output of the inverter 812 is set to the substrate potential VDD. Then, the nMOS transistor N205 is turned off, so that the data output line DL is held at the power supply voltage VDD.
When a write operation is performed, the write control signal /WE is set to the low level (or the substrate potential GND). Then, in the bit line pair selection circuit 802, values of the write data signal lines WDT and WDN are output to the bit line pair BLT and BLN selected by the bit line pair selection signal /YS that is in an active state. That is, when the bit line pair selection signal /YS is at a low level and the write control signal /WE is at a low level, an output of the NOR circuit 811 becomes the high level (or the power supply voltage VDD). The nMOS transistors N101 and N102 that receive the output of the NOR circuit 811 are both turned on. Then, signal levels of a pair of the complementary write data signal lines WDT and WDN are transferred to the bit line pair BLT and BLN, respectively.
When the read operation or the write operation is completed, the pre-charge control signal PC is set to the low level. The pMOS transistors P101 to P103 are then turned on, and the bit line pair BLT and BLN is charged to the power supply voltage VDD.
Non-patent Document 1:
“A 2-GHz cycle, 430-ps access time 34-kb L1 directory SRAM in 1.5 V, 0.18-um CMOS bulk technology”, R. V. Joshi, 2000 Symposia on VLSI circuit, pp. 222-225